It is well known that integrated circuits (also referred to as “chips”) are coupled to a printed circuit board via a package. FIG. 1A is a simplified side view of a prior art integrated circuit 12P and a prior art, four layer package 16P. In this embodiment, the package 16P includes a top bump array 19P having a plurality of bumps that electrically and mechanically attach the chip 12P to the top of the package 16P. FIG. 1B is a simplified view of a prior art bump array 19P. In this embodiment, the bump array 19P includes (i) a plurality of positive terminal bumps 42P (labeled with “+”) and a plurality of negative terminal bumps 44P (labeled with “−”) that are located near the center of the bump array 19P, and (ii) a plurality of signal bumps 46P (labeled with “s”) that are positioned around an outer periphery of the bump array 19P.
Additionally, referring back to FIG. 1A, the package 16P can include one or more decoupling capacitors 38P that are placed on the top of the package 16P, and a plurality of conductive layers 20P that are separated by insulating layers 22P. The decoupling capacitors 38P help stabilize the voltage delivered to the integrated circuit 12P. For example, when there is a sudden change in the current drawn by the integrated circuit 12P, the decoupling capacitors 38P provide a local source of charge so that the current can be supplied quickly without allowing the voltage across the positive and negative terminals to dip suddenly.
Each of the decoupling capacitors 38P includes a positive capacitor pad and a negative capacitor pad. In one design, (i) a top, first conductive layer 20AP is electrically connected to the signal bumps 46P, (ii) a second conductive layer 20BP (that is positioned below the first conductive layer 20AP) is connected to the negative terminal bumps 44P and the negative capacitor pad with one or more vias, (iii) a third conductive layer 20CP (that is positioned below the second conductive layer 20BP) is connected to the positive capacitor pad and the signal power 42P, and (iv) a fourth conductive layer 20DP (that is positioned below the third conductive layer 20CP) is connected to a pinout 16BP.
Unfortunately, with this arrangement, an electrical path 15P (illustrated with thick dashed line) of the capacitors 38P to the terminal bumps 42P, 44P is relatively long, has relatively high impedance, and has a relatively high loop inductance. As a result thereof, the capacitors 38P may not effectively provide power to the terminal bumps 42P, 44P. Stated in another fashion, the inadequate decoupling of the capacitors 38P leads to excessive power supply noise. This can adversely influence signal integrity, cause EMC problems, and ultimately adversely influencing the reliability of the product.